Electronic systems may be operated in environments and/or in circuits where they have the potential to be exposed to a transient electrical event that is an electrical signal of relatively short duration but having a high or rapidly changing voltage that exceeds the normal operating voltage for that electronic system. Transient electrical events can include, for example, electrostatic discharge events arising from the abrupt release of charge from an object or person to an electronic circuit. Such electrostatic discharge (ESD) or electrical over stress (EOS) events may include “body” discharge events and “machine” discharge events. Various organizations, such as the Joint Electronic Device Engineering Council (JEDEC), the International Electrotechnical Commission (IEC), the Automotive Engineering Council (AEC), and the International Organization for Standardization (ISO), set standards for such discharge events.
Body discharge events describe the ESD events where a person who has become charged may discharge their electrostatic charge through contact with an electronic circuit. Such events are measured, for example, by looking at the circuit performance one hundred nanoseconds after the initiation of the discharge event. Machine events such as the IEC charged device model (IECCDM) measure device performance after a period of around 600 picoseconds after initiation of the discharge. Such short time scale ESD events may give rise to gate oxide damage in metal oxide semiconductor field effect transistors (MOSFETs), or to junction damage or charge trapping within integrated circuits. Furthermore, even if the transient event does not induce physical damage to the device, it may induce latch up (the inadvertent creation of a low impedance path) thereby disrupting the functioning of the integrated circuit and potentially giving rise to permanent damage to the integrated circuit from self-heating in the latch up current path. There is therefore a need to provide an integrated circuit with protection from transient electrical events.
It is also desirable to provide overvoltage protection circuits that have a controllable trigger voltage and a controllable “snap back” voltage which represents a holding voltage. Overvoltage protection circuits can be provided with a holding voltage that is less than the trigger voltage but greater than the device supply rail voltage.